• 0 Posts
  • 19 Comments
Joined 2 years ago
cake
Cake day: September 29th, 2023

help-circle













  • Use tailscale for host nodes, use tailscale docker container in a compose stack with an app that you sidecar to. That way that app is on your tailnet as if it is its own computer. Use tailscale serve for reverse proxying support of the apps. Then, setup a vps node (I use linodes $5 node) with tailscale and configure that to be your DMZ into your tailnet.

    For DMZ, use Caddy, UFW, and fail2ban. Also take advantage of ACLs in the Tailscale admin console to only have the VPS able to route traffic to specific apps you want to expose. My current project is to work in Authelia into this setup so a user logs into one exposed app and is able to traverse to other exposed apps through header / token authentication.

    Oh also, segment the tailnet using different authentication keys. Each host node should have its own key, all the apps on a host node should have a shared key, and all public facing clients should have a common shared key. That way in case of compromise you can revoke the affected keys without bringing down your network.



  • Not really, HDL is HDL. At the end of the day, as long as you know what you want to do electrically then everything else is an exercise of translating that desire into VHDL, Verilog, or SystemVerilog. The only real hassle is creating test-benches and verification simulations. But at that point it’s discretionary towards the designer. A lot of tools coming from Intel, Xilinx, and Synopsys allow you to “black box” components. So a module written in VHDL can be incorporated into a design or test bench written in verilog and vis-versa. IMHO VHDL is still dominant because grey beard chief engineers throw a little hissy fit at design reviews when they learn the junior engineers did everything in verilog.


  • A ton of people. Anything aerospace, DoD, Space, or critical infrastructure. All those industries have to use VHDL to support legacy products from the 80s and 90s. At that point everyone is like, “Sure its 2025, by why switch to SystemVerilog? We already know VHDL.” and thus you got a whole army of engineers making next gen satellites, augmented reality headsets, etc. …… in VHDL 93.